Contacts:

Challenges in Device Scaling -
Equipment and Materials Challenges for 45 and 32 nm

Location: North Hall.

The Tom Bailey CCM presentation will be on Wed July 12 at 11:40am (~20 min presentation).

Here are the details for the specific session that includes our presentation:

Wednesday July 12, 2006
Interconnect Technology for 45 and 32 nm
Copper interconnect technology is evolving rapidly with ultra thin barrier layers, better controlled metal disposition, advanced planarization processes, and new dielectric materials, but is it enough?
Will the industry be forced to go to 3D architecture to meet performance requirements?

Session Chair: Ken Monnig, AMD
11:00am-11:20am AMD, Cathy Labelle - Challenges and Opportunities in
Implementation and Selection of New Materials
11:20am-11:40am SEZ, Ernst Gaulhofer - Surface Preparation Challenges for 45 and 32 nm
11:40am-12:00pm Metara, Tom Bailey - Copper Process Control
12:00pm-12:20pm Cabot Microelectronics Corporation, Paul Feeney - Planarization
Challenges for Sub 65 nm Technologies

Details on this session can be found on the SEMICON WEST website:
http://wps2a.semi.org/wps/portal/_pagr/123/_pa.123/334?&dFormat=application/msword&docName=P037317